(1) Field of the Invention
This invention relates to semiconductor memory devices, and more particularly to semiconductor memory devices, in which the speed grade of synchronous DRAM, synchronous SRAM, etc. synchronized to an external clock is improved when the Column Address Strobe (CAS) latency is 2.
(2) Description of the Related Art
Some prior art semiconductor devices of this type are shown in "NEC Technical Reports", Vol. 47, No. 3, 1994, pp. 76-77. FIGS. 1A and 1B are timing charts of operation of the synchronous DRAM in the literature, FIG. 1A being for the case when the CAS latency is 3, and FIG. 1B being for the case when the CAS latency is 2. FIG. 1C is a timing chart of operation of a general purpose DRAM corresponding to the timing charts in FIGS. 1A and 1B. Referring to FIGS. 1A to 1C, external signals, for instance, a command signal (COMMAND) and an external address signal (ADD) are latched in synchronism to the rise timing of a clock signal from low level to high level, the latched signals being decoded to be recognized as respective commands.
The term "CAS latency" herein refers to the necessary number of clock cycles from the designation of column address (READ command input) till the outputting of the designated address data. For example, referring to FIG. 1A, in clock cycle C6 that is delayed two clock cycles after clock cycle C4 of clock signal for synchronizing the READ command input, data of internal address signal A1 turns to be outputted as the first output data, and a memory system latches and outputs this data at the rise timing of clock cycle C7 delayed three clock cycles, thus providing CAS latency of 3. In subsequent clock cycles C8 to C10, data of internal addresses A2 to A4 generated in an internal counter, i.e., a burst counter, are outputted.
In the case of FIG. 1B, in clock cycle C5 two clock cycles delayed after clock cycle C3 of the clock signal for synchronizing the READ command, data of address A1 is outputted to provide CAS latency of 2.
The fact that in the synchronous DRAM a row address signal (ROW) and an active command (ACT) are supplied in synchronism to clock cycle C1 of the clock signal, corresponds in the general purpose DRAM to Row Address Strobe (RAS) inversion signal in clock cycle C1 from high level to low level, and a word line for taking out the low address signal is selected, thereby amplifying the memory cell data in a sense amplifier.
The supplying of the external address signal A1 and the READ command in synchronism to clock cycle C1 corresponds in the general purpose DRAM to the supplying of the external address signal A1 and the inverting of the CAS inversion signal from high level to low level in clock cycle C4, and data of address A1 is read out as shown in FIG. 1C.
The supplying of a precharge command (PRE) in synchronism to clock cycle C13 corresponds, in the general purpose DRAM, to the inverting of the RAS inversion signal from low level to high level in clock cycle C13.
The speed grade which represents the typical operation speed of the current general purpose DRAM is -60. In this grade, time from the external address signal input till the output of data stored in a memory cell from an output buffer, i.e., address access time, is 30 nsec. In the case of the synchronous DRAM, on the other hand, the internal operation from the supply of the READ command till the output of the memory cell data from the output buffer, corresponds to the operation in the address access time of the general purpose DRAM.
Thus, when the CAS latency is 3, an internal operation for 30 nsec. is performed in three clock cycles. This means that the minimum clock cycle period of 10 nsec., and the maximum frequency is 100 MHz.
Considering, for instance, a case when it is desired to operate the synchronous DRAM with a minimum clock cycle of 15 nsec., i.e., at a relatively low frequency of 67 MHz, it corresponds to 45 nsec. in three clocks. As described before, inside the synchronous DRAM, as for the operation speed power the minimum clock cycle is 10 nsec., and three clocks corresponds to 30 nsec. Therefore, the longer time of 45 nsec. is outside the subject of consideration.
Therefore, when an operation mode is set such that data of internal address signal A1 begins to be outputted from the next clock (i.e., first clock) to the clock signal at the timing when the READ command is supplied, that is, when a mode is set to CAS latency of 2, the minimum clock cycle becomes 15 nsec. with two clocks becoming 30 nsec. The maximum frequency is thus 67 MHz. It is thus possible to increase the system effect.
When a 100 MHz operation with CAS latency of 3 and a 67 MHz operation with CAS latency of 2 are considered as internal operations in the device, they are substantially at the same internal operation speed.
In other words, when the CAS latency is 3, the three clock cycles correspond to 3.times.10=30 nsec., while with CAS latency of two clock cycles correspond to 2.times.15=30 nsec.
FIG. 2 is schematic representation of a prior art example of semiconductor memory device. This memory device adopts a three-stage pipeline system, in which the flow of signal from the supply of an external address signal till the memory data output from the output buffer, i.e., the address access bus, is divided by three latch circuits.
This semiconductor memory device comprises an input buffer 1 for receiving an external address signal supplied from an input terminal 17; a burst counter 2 for latching the external address signal output in synchronism to a clock signal supplied from a terminal 18 through buffer 10, thus generating internal addresses A1, A2, A3, . . . , a column decoder 3 including NAND gates 31a, 31b, . . . , for decoding the data output of the burst counter 2; a column switch latch portion 4 including a plurality of latch elements each having a switch 41a and inverters 42a and 43a, for latching the column decoder output in synchronism to a control signal which is outputted from an OR gate 11 for taking logical sum (OR operation) of the clock signal and an internally supplied mode signal 19; a memory block 5; a column selector constituting the memory block 5 and including a series circuit having a transistor 51a with a column selection signal 23 coupled thereto and a transistor 52a with one sense amplifier output coupled thereto at the gate, and another series circuit having a transistor 51b with the column selection signal coupled thereto and a transistor 52b with the other sense amplifier output coupled thereto at the gate, these series circuits being connected between a power supply potential VDD and the ground potential; a sense amplifier 53 for amplifying cell data supplied from pair digit lines 30 and 31; a cell 54 provided at an intersection of a word line 29 crossing the digit lines 30 and 31; read buses 25 and 26 for transferring cell data, which are pulled up by load elements 34 and 35, respectively, to the power supply potential VDD; data amplifiers 6 and 7 for amplifying the cell data on the read buses 25 and 26; an output data latch circuit 8 for latching the cell data supplied on the read/write buses 32 and 33 in synchronism to a clock signal supplied from the clock signal terminal 18 through the buffer 50; and an output buffer 9 for outputting the output data through an output terminal 20 to the outside.
The column decoder 3, column switch latch portion 4 and memory clock 5 are shown only partly for facilitating the description.
In the illustration of the above structure, a portion from the burst counter 2 to the column switch latch portion 4 is shown as a first stage 36 of pipeline, a portion from the column switch latch portion 4 to the output data latch circuit 8 is shown as a second stage 37 of pipeline, and a portion from the output data latch circuit 8 to the output terminal 20 is shown as a third stage 38 of pipeline.
FIGS. 3A and 3B are timing charts for describing the operation of the above FIG. 2 structure, FIG. 3A being for a case when the CAS latency is 3, and FIG. 5B being for a case when the CAS latency is 2.
In the first stage 36 of pipeline, in clock cycle C1 of the clock signal, the burst counter 2 latches external address signal A1, and generates and outputs internal address signals A1, A2, A3, . . . which are decoded in the column decoder 3.
In the case when the CAS latency is 3, with the mode signal 19 in low level, in the second stage 37 of pipeline in the next clock cycle C2, the output of the column decoder 3 is latched in synchronism to the clock signal on the control signal line 27, and by this latched output signal which is at high level, the transistors 51a and 51b of the memory block 5 are selected.
At this time, the word line 29 that is selected by an active command and a row address (ROW) (both being not shown) allows memory cell data to be read out onto the pair digit lines 30 and 31. The data thus read out is amplified in the sense amplifier 53 to render one of the pair digit lines 30 and 31 to be at high level and the other at low level. By this high level, for instance, the transistor 2a is activated and then the transistors 51a and 51b are activated. The read bus 25 to which the activated transistor 51a is connected becomes low level. The read bus 26 to which the non-activated transistor 51b is connected becomes high level because it is pulled up to the power source potential VDD by the load element 34. These data are amplified by the data amplifiers 6 and 7 so as to be supplied to the output latch circuit 8.
Then, in the third stage 38 of pipeline, in the next clock cycle C3, the output latch circuit 8 latches data supplied in synchronism to the clock signal on the control signal line 28, and outputs the latched data to the outside through the output buffer 9.
In the case when the CAS latency is 2, the operation in completed in two clock cycles as mentioned above. To this end, the mode signal 19 becomes high level to forcibly fix the output of the OR gate 11 to high level, and the second stage of pipeline is not latched but is brought to a state in which data is outputted by inversion only. That is, the first and second stages of pipeline are coupled together and operated in one clock cycle, thereby realizing the CAS latency of 2.
In the above semiconductor memory device, the signal processing times or capacities of the first stage, the second stage and the third stage of pipeline are about 7, 10 and 10 nsec., respectively. Thus, when the CAS latency is 3, the minimum clock cycle that is necessary for obtaining the operation of all the pipeline stages is 10 nsec., that is, the corresponding maximum frequency is 100 MHz.
When the CAS latency is 2, the first and second stages of pipeline are coupled together for one clock cycle operation. Thus, in this case the minimum clock cycle necessary for the operation of all the pipeline stages is 7+10=17 nsec., and the corresponding maximum frequency is 59 MHz.
As described before, when the speed grade representing the typical operation speed of the current general purpose DRAM is -60, the time from the inputting of the external address signal till the outputting of data stored in the memory cell from the output buffer, i.e., the address access time, is 30 nsec. On the other hand, the internal operation of the synchronous DRAM from the supplying of the READ command till the outputting of the memory cell data from the output buffer, corresponds to the operation of the general purpose DRAM in the address access time thereof.
Therefore, in comparison to the case when it is desired to operate the synchronous DRAM in the same minimum clock cycle of 15 nsec. as in the general purpose DRAM, i.e., at the corresponding relatively low frequency of 67 MHz, when the CAS latency is 2, the minimum clock cycle is 7 nsec., and the maximum frequency is 59 MHz. The operation speed is therefore extremely reduced with the same speed grade.
In other words, the CAS latency of 2 determines the upper limit of the speed grade, resulting in an operation speed deterioration as great as about 15%, and therefore it is impossible to attain the desired speed grade.